The invention is generally related to the field of semiconductor devices and more specifically to multi-layered polysilicon process for reducing gate capacitance.
There are a number of extrinsic capacitances associated with a MOS transistor. A typical MOS transistor is shown in FIG. 1. An gate dielectric 20 is formed on a semiconductor substrate and a transistor gate 30 is formed on the gate dielectric 20. Following the formation of the transistor gate 30, ion implantation is used to form the drain and source extension regions 40 in the substrate. Sidewall structures 50 are then formed adjacent to the gate 30 and the source and drain regions 60 are then formed by ion implantation. During the subsequent high temperature anneal, necessary to activate the implanted dopants, lateral diffusion of the implanted species will result in the formation of the overlap regions 70 shown in FIG. 1. These overlap regions 70 gives rise to xe2x80x9coverlap capacitancesxe2x80x9d. The value of these overlap capacitances depends on the thickness of the gate dielectric 20 in the region of overlap 70 as well as the area of the overlap region. As the area of the transistor gate 30 is reduced, this overlap capacitance becomes a larger percentage of the total overall transistor capacitance resulting in a reduction in transistor and integrated circuit performance. A number of different techniques are current being used to reduce this overlap capacitance. These include the use of silicon oxide spacers between the transistor gate 30 and the sidewall structures 50 and the formation of a notch at the bottom of the transistor gate adjacent to the gate dielectric 20. The current methods used to form the notch involve timed etches which are unreliable, not easily controlled, and not very reproducible. The size of the transistor gate is the most critical parameter in determining transistor performance and reliability and as such any processing technique which varies the size of the transistor gate must be precisely controllable, reproducible, and reliable. There is therefore a great need for a method of forming a notch on a transistor gate that is precisely controllable, reproducible, and reliable.
The instant invention describes a method for forming a notched gate for MOS transistors. The method comprises forming a multi-layered gate structure comprised of layers with differing oxidation rates. The oxidation rates of the various layers are varied by the incorporation of an oxidation rate retardant such as carbon and nitrogen or a species that will enhance the oxidation rate such as chlorine or fluorine. Thermal oxidation processes after gate etch will result in the formation of a notched gate structure. The notched gate method of the instant invention is precisely controllable resulting in increased uniformity compared to existing methods.